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sy89846u 1.5g hz precision, lvpecl 1:5 fanout with 2:1 mux and fail safe input with internal termination precision edge ? precision edge is a registered trademark of micrel, inc . micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com oct. 1, 2013 m9999-072211b hbwhelp@micrel.com or (408) 955-1690 general description the sy89846u is a 2.5/3.3v, 1:5 lvpecl fanout buffer with a 2:1 differential input multiplexer (mux). a unique fail-safe input (fsi) protection prevents metastable output conditions when the selected input clock fails to a dc voltage (voltage between the pins of the differential input drops significantly below 100mv). the differential input includes micrels unique, 3 -pin internal termination architecture that can interface to any differential signal (ac- or dc-coupled) as small as 100mv (200mv pp ) without any level shifting or termination resistor networks in the signal path. the ou tputs are 800mv, lvpecl with fast rise/fall times guaranteed to be less than 250ps. the sy89846u operates from a 2.5v 5% or 3.3v 10% supply and is guaranteed over the full industrial temperature range of C 40c to +85c. the sy89846u is part of micrels high -speed, precision edge ? product line. all support documentation can be found on mi crels web site at: www.micrel.c om . functional block diagram precision edge ? features ? selects between two inputs, and provides 5 precision lvpecl copies ? fail-safe input C prevents outputs from oscillating when input is invalid ? guaranteed ac performance over temperature and supply voltage: C dc -to >1.5ghz throughput C < 900ps propagation delay (in- to - q) C < 250ps rise/fall times ? ultra-low jitter design: C 150fs rms phase jitter (typ) C 0.7ps rms mux crosstalk induced jitter ? unique, patented mux input isolation design minimizes adjacent channel crosstalk ? unique patented internal termination and vt pin accepts dc- and ac-coupled inputs (cml, pecl, lvds) ? wide input voltage range. vcc to gnd ? 2.5v 5% or 3.3 10% supply voltage ? -40c to +85c industrial temperature range ? available in 32-pin (5mm x 5mm) qfn package applications ? fail-safe clock protection ? sonet clock distribution ? backplane distribution markets ? lan/wan ? enterprise servers ? ate ? test and measurement downloaded from: http:///
micrel, inc. sy89846u oct. 1, 2013 m99 99 -072211b hbwhelp@micrel.com or (408) 955-1690 2 ordering information ( 1) part number package type operating range package marking lead finish SY89846UMG qfn- 32 industrial sy89846u with pb -free bar-line indicator nipdau pb -free SY89846UMGtr (2) qfn- 32 industrial sy89846u with pb -free bar-line indicator nipdau pb -free notes: 1. contact factory for die availability. dice are guarantee d at t a = 25c, dc electricals only. 2. tape and reel. pin configuration 32 -pin qfn (qfn- 32) downloaded from: http:///
micrel, inc. sy89846u oct. 1, 2013 m99 99 -072211b hbwhelp@micrel.com or (408) 955-1690 3 pin description pin number pin name pin function 1,8 vt0, vt1 input termination center-tap: each side of a differential input p air terminates to the vt pin. the vt pin provides a center-tap for each input (in, /in) to a termination network for maximum interface flexibility. see input inte rface applications subsection. 2, 3 6, 7 in0, /in0 in1, /in1 differential inputs: these input pairs are the differential signal inputs to the device. these inputs accept ac- or dc-coupled signals as small as 1 00mv. the input pairs internally terminate to a vt pin through 50?. each input has l evel shifting resistors of 3.72k ? to vcc. this allows a wide input voltage range from vcc to gnd. see figure 3a, simplified differential input stage for details. not e that these inputs will default to a valid (either high or low) state if left op en. see input interface applications subsection. 10, 11, 30, 31 gnd, exposed pad ground. exposed pad must be connected to a ground plane that is the same potential as the ground pins. 4 oe single-ended input: this ttl/cmos input disables and enables the q0-q4 outputs. it is internally connected to a 25k ? pull-up resistor and will default to a logic high state if left open. when disabled, q goes low and /q goes high. oe being synchronous, outputs will be enabled/disabled followin g a rising and a falling edge of the input clock. v th = v cc /2. 5 sel single-ended input: this single-ended ttl/cmos-compatible inp ut selects the inputs to the multiplexer. note that this input is internally conn ected to a 25k? pull - up resistor and will default to logic high state if left open. v th = v cc /2 . 9, 32 vref-ac1 vref-ac0 reference voltage: these outputs bias to v cc C 1.2v. they are used for ac- coupling inputs in and /in. connect vref-ac directly to the correspondi ng vt pin. bypass with 0.01f low esr capacitor to vcc. due to limited drive capability, the vref-ac pin is only intended to drive its respective vt pin. maximum sink/source current is 0.5ma. see input interface applications subsection. 12, 13, 16, 19, 22, 25, 28, 29 vcc positive power supply: bypass with 0.1f || 0.01f low esr capacitors as close to the v cc pins as possible. 27, 26 24, 23 21, 20 18, 17 15, 14 q0, /q0 q1, /q1 q2, /q2 q3, /q3 q4, /q4 lvpecl differential output pairs : d ifferential buffered output copies of the selected input signal. the output swing is typically 800mv. un used output pairs may be le ft floating with no impact on jitter. see lvpecl output termination subsection. normally terminated with 50? to v cc -2v. these differential lvpecl outputs are a logic function of the in0, in1, and sel inputs. see truth table below . truth table inputs outputs in0 /in0 in1 /in1 sel q /q 0 1 x x 0 0 1 1 0 x x 0 1 0 x x 0 1 1 0 1 x x 1 0 1 1 0 downloaded from: http:///
micrel, inc. sy89846u oct. 1, 2013 m99 99 -072211b hbwhelp@micrel.com or (408) 955-1690 4 absolute maximum ratings ( 1) supply voltage (v cc ) .......................... C 0.5v to +4.0v input voltage (v in ) .................................. C 0.5v to v cc lvpecl output current (i out ) continuous .................................................. 50ma surge ......................................................... 100ma current (v t ) source or sink on vt pin ......................... 100ma input current source or sink current on (in, /in) ............ 50 ma current (v ref ) source or sink current on v ref - ac (4) .......... 0.5ma maximum operating junction temperature ..... 125c lead temperature (soldering, 20sec.) ............. 260c storage temperature (t s ) ................ C 65c to +150c operating ratings ( 2) supply voltage (v cc ) .................. +2.375v to +2.625v ..................................................... +3.0v to +3.6v ambient temperature (t a ) ................ C 40c to +85c package thermal resistance (3) qfn ( ? ja ) still- air ..................................................... 50c/w qfn ( ? jb ) junction- to -board .................................... 31 c/w dc electrical characteristics (5) t a = C 40c to +85c, unless otherwise stated. symbol parameter co ndition min typ max units v cc power supply voltage 2.375 3.0 2.5 3.3 2.625 3.6 v v i cc power supply current no load, max v cc 60 75 ma r in input resistance (in- to -v t ) 45 50 55 ? r diff_in differential input resistance (in- to -/in) 90 100 110 ? v ih in put high voltage (in, /in) 0.1 v cc v v il input low voltage (in, /in) 0 v ih C 0.1 v v in input voltage swing (in, /in) see figure 2a. note 6 0.1 1.0 v v diff_in differential input voltage swing |in-/in| see figure 2b. 0.2 1.9 v v in_fsi input voltage threshold that triggers fsi 30 100 mv v ref- ac output reference voltage i vref-ac = + 0.5ma v cc C 1.3 v cc C 1.2 v cc C 1.1 v v t_in voltage from input to v t 1.28 v notes: 1. permanent device damage may occur if absolute maximu m ratings are exceeded. this is a stress rating only and fu nctional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to a bsolute maximum rating conditions for extended periods may affect device reliabilit y. 2. the data sheet limits are not guaranteed if the device i s operated beyond the operating ratings. 3. package thermal resistance assumes exposed pad is solde red (or equivalent) to the devices most negative potential on the pcb. ? ja and ? jb values are determined for a 4-layer board in still air unless otherwise stated. 4. due to the limited drive capability, use for input of the same package only. 5. the circuit is designed to meet the dc specifications sh own in the above table after thermal equilibrium has been es tablished. 6. v in (max) is specified when v t is floating. downloaded from: http:///
micrel, inc. sy89846u oct. 1, 2013 m99 99 -072211b hbwhelp@micrel.com or (408) 955-1690 5 lvpecl outputs dc electrical characteristics (7) v cc = 2.5v 5% or 3.3v 10%; r l = 50? to v cc -2v; t a = C 40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units v oh output high voltage q, /q v cc -1.145 v cc -0.895 v v ol output low voltage q, /q v cc -1.945 v cc -1.695 v v out output voltage swing see figure 2a. 550 800 950 mv v diff_out differential output voltage swing see figure 2b. 1100 1600 1900 mv lvttl/cmos dc electrical characteristics (7) v cc = 2.5v 5% or 3.3v 10%; t a = C 40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current - 125 30 a i il input low current - 300 a note: 7. the circuit is designed to meet the dc specifications sh own in the above table after thermal equilibrium has been es tablished. downloaded from: http:///
micrel, inc. sy89846u oct. 1, 2013 m99 99 -072211b hbwhelp@micrel.com or (408) 955-1690 6 ac electrical characteristics (8) v cc = 2.5v 5% or 3.3v 10%; r l = 50? to v cc -2v; input t r /t f < 300ps; t a = C 40c to + 85c, unless otherwise stated . symbol parameter condition min typ max units f max maximum operating frequency v out 400mv, v in 200mv 1.5 2.0 ghz v out 400mv, v in 100mv 1 .0 1.5 ghz t pd differential propagation delay in - to -q 100mv < v in 200mv, note 9 600 850 1100 ps in- to -q 200mv < v in 800mv, note 9 400 700 900 ps sel - to -q v th = v cc /2 350 600 800 ps t s oe set-up time oe - to - in note 10 300 ps t h oe hold time in - to - oe note 10 800 ps t skew output- to -output skew note 11 7 20 ps input- to -input skew note 12 5 15 ps part- to -part skew note 13 300 ps t jitter rms phase jitter output = 622mhz 150 fs integration range 12khz C 20mhz crosstalk-induced jitter note 14 0.7 ps rms t r, t f output rise/fall time (20% to 80%) at full output swing. 110 170 250 ps duty cycle v in > 200mv 47 53 % 100mv < v in 200mv 45 55 % notes: 8. high-frequency ac-parameters are guaranteed by des ign and characterization. 9. propagation delay is measured with input t r , t f 300ps (20% to 80%). the propagation delay is a function of the rise and fall times at in. see typical operating characteristics for details. 10 . set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. for asynchronous applications, set-up and hold do not apply. 11 . output- to -output skew is measured between two different outputs under identical transitions. 12 . input- to -input skew is the time difference between the two inpu ts to one output, under identical input transitions. 13 . part- to -part skew is defined for two parts with identical power s upply voltages at the same temperature and with no skew of the edges at the respective inputs. 14 . crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchrono us with respect to each other at the inputs. downloaded from: http:///
micrel, inc. sy89846u oct. 1, 2013 m99 99 -072211b hbwhelp@micrel.com or (408) 955-1690 7 functional description clock select (sel) sel is an asynchronous ttl/cmos compatible input that selects one of the two input signals. an internal 25k? pull -up resistor defaults the input to logic high if left open. input switching threshold is v cc /2. refer to figure 1a. fail-safe input (fsi) the input includes a special fail-safe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mv pk (200mv pp ), typically 30mv pk . maximum frequency of the sy89846u is limited by the fsi function. refer to figure 1b. input clock failure case if the input clock fails to a floating, static, or extremely low signal swing such that the voltage swing across the input pair is significantly less than 100mv, fsi function will eliminate a metastable condition and latch the outputs to the last valid state. no ringing and no undetermined state will occur at the output under these conditions. the output recovers to normal operation once the input signal returns to a valid state with a typical swing greater than 30mv. note that the fsi function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. due to the fsi function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. refer to typical opera ting characteristics for detailed information. output enable (oe) oe is a synchronous ttl/cmos compatible input that enables/disables the outputs based on the input to this pin. the enable function is synchronous so that the clock outputs will be enabled or disabled following a rising and a falling edge of the input clock. refer to figure 1c. internal 25k? pull -up resistor defaults the input to logic high if left open. input switching threshold is v cc /2. downloaded from: http:///
micrel, inc. sy89846u oct. 1, 2013 m99 99 -072211b hbwhelp@micrel.com or (408) 955-1690 8 timing diagrams figure 1a. sel- to -q delay figure 1b. fail safe feature downloaded from: http:///
micrel, inc. sy89846u oct. 1, 2013 m99 99 -072211b hbwhelp@micrel.com or (408) 955-1690 9 timing diagrams (continued) figure 1c. enable output timing diagram figure 1d. propagation delay figure 1e. setup and hold time downloaded from: http:///
micrel, inc. sy89846u oct. 1, 2013 m99 99 -072211b hbwhelp@micrel.com or (408) 955-1690 10 typical operating characteristics v cc = 3.3v, gnd = 0v, t r / t f 300ps, v in = 100mv, r l = 50? to v cc C 2v; t a = 25c, unless otherwise stated. downloaded from: http:///
micrel, inc. sy89846u oct. 1, 2013 m99 99 -072211b hbwhelp@micrel.com or (408) 955-1690 11 functional ch aracteristics v cc = 3.3v, gnd = 0v, v in 400mv, t r /t f 300ps, r l = 50? to v cc -2v; t a = 25c, unless otherwise stated. downloaded from: http:///
micrel, inc. sy89846u oct. 1, 2013 m99 99 -072211b hbwhelp@micrel.com or (408) 955-1690 12 single -ended and differential swings figure 2a. single-ended voltage swing figure 2b. differential voltage swing in put and output stages figure 3a. simplified differential input stage figure 3b. simplified differential output stage downloaded from: http:///
micrel, inc. sy89846u oct. 1, 2013 m99 99 -072211b hbwhelp@micrel.com or (408) 955-1690 13 input interface applications figure 4a. lvpecl interface (dc-coupled) figure 4b. lvpecl interface (ac-coupled) option: may connect v t to v cc figure 4c. cml interface (dc-coupled) figure 4d. cml interface (ac-coupled) figure 4e. lvds interface (dc-coupled) downloaded from: http:///
micrel, inc. sy89846u oct. 1, 2013 m99 99 -072211b hbwhelp@micrel.com or (408) 955-1690 14 pecl output interface applications pecl has a high input impedance, a very low output impedance (open emitter), and a small signal swing which results in low emi. pecl is ideal for driving 50 ? - and 100 ? -controlled impedance transmission lines. there are several techniques for terminating the pecl output: parallel termination-thevenin equivalent, parallel termination (3-resistor), and ac- coupled termination. unused output pairs may be left floating. however, single-ended outputs must be terminated, or balanced. figure 5a. parallel termination-thevenin equivalent figure 5b. parallel termination (3 -resistor) related product and support documentation part number function data sheet link sy89847u precision lvds 1 :5 fanout with 2 :1 mux and fail-safe input with internal termination www.micrel.com/product-info/products/sy89847u.shtml . qfn application note www.amkor.com/products/notes_papers/mlfappnote.pdf hbw solutions new products and applications www.micrel.com/product-info/products/solutions.shtml downloaded from: http:///
micrel, inc. sy89846u oct. 1, 2013 m99 99 -072211b hbwhelp@micrel.com or (408) 955-1690 15 package information 32 -pin (5mm x 5mm) qfn packages notes: 1. package meets level 2 moisture sensitivity classification . 2. all parts are dry-packed before shipment. 3. exposed pad must be soldered to a ground for proper thermal management. micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is believ ed to be accurate and reliable. however, no responsibilit y is assumed by micrel for its use. micrel reserves the right to change circuit ry and specifications at any time without notification t o the custome r. micrel products are not designed or authorized for use a s components in life support appliances, devices or sys tems where malfunction of a product can reasonably be expected to result in person al injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sust ain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchasers use or sale of micrel products for use in life support appliances, devic es or s ystems is a purchasers own risk and purchaser agrees to fully inde mnify micrel for any damages resulting from such use or sale. ? 2006 micrel, inc. downloaded from: http:///

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